1. Field of the Invention
This present invention relates generally to the field of integrated circuit manufacturing technology and, more specifically, to reducing the standard deviation of the critical dimensions of integrated circuit structures.
2. Description of the Related Art
This section is intended to introduce the reader to aspects of the art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In the manufacturing of integrated circuits, numerous microelectronic circuits are simultaneously manufactured on a semiconductor substrate. These substrates are usually referred to as wafers. A typical wafer is comprised of a number of different regions, known as die regions. When fabrication is complete, the wafer is cut along these die regions to form individual dies. Each die contains at least one microelectronic circuit, which is typically replicated on each die. Examples of microelectronic circuits that may be fabricated in this manner include circuits such as dynamic random access memories and microprocessors.
Integrated circuits, such as memory devices, are typically fabricated on a wafer surface using a variety of manufacturing processes, such as layering, doping, and patterning. Layering generally refers to adding material to the surface of the wafer by a growth process, such as oxidation, or through a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). Doping generally refers to the process of implanting dopants into the wafer surface or overlying layer and may be used to increase the current carrying capacity of a region of the wafer or overlying layer of material. The doping process may be implemented before a layer is formed, between layers, or even after the layer is formed. Generally, the doping process may be accomplished through an ion implantation process or through thermal diffusion, for example.
Patterning refers to a series of steps that result in the removal of selected portions of layers or underlying wafer material. After removal of the selected portions of the one or more layers via a wet or dry etch process, a pattern is left on the wafer surface. The removal of material allows the structure of the device to be formed by providing holes or windows between layers or by removing unwanted layers. Patterning sets the critical dimensions of the integrated circuit structures being fabricated. Critical dimensions of an integrated circuit include the widths of the lines and spaces of circuit patterns in addition to the area of the contacts. These critical dimensions govern the electrical characteristics of the integrated circuit. Disadvantageously, errors in the patterning and removal process may affect the critical dimensions of the integrated circuit, and may result in changes and failures in the electrical characteristics in the device.
One commonly used patterning technique is photolithography. One of the objectives of photolithography is to transfer a well-defined pattern to the surface of a wafer with minimal ambiguities or anomalies. In using photolithography, a pattern may be formed by using a photomask to expose certain regions of a radiation sensitive material, typically referred to as photoresist, to a certain wavelength of light. Typically, the radiation source provides UV light to pattern the photoresist. However, certain photoresists may also be implemented using other energy types, such as X-rays. Exposure to the radiation changes the structure of the photoresist. If the photoresist is a negative photoresist, then the photoresist becomes polymerized where it is exposed. If the photoresist is a positive photoresist, the exposed region of photoresist becomes divided or softened. After the exposure to the radiation, the unpolymerized regions may be dissolved by applying an appropriate solvent or it may be removed through a plasma etch process.
To enhance the photolithographic process, a bottom anti-reflective coating (BARC) layer may be implemented underneath the photoresist. The BARC layer absorbs the radiation generated by the source, thereby reducing development of the photoresist caused by reflections from underlying layers. By providing an underlying layer for absorbing the radiation, the patterned structure, which may partially determine the critical dimensions of one or more integrated circuits, is typically more defined with fewer defects as compared to methods wherein a BARC layer is not used. Once the photoresist has been patterned, the photoresist layer may be removed to allow the underlying structure to be processed. While it may be desirable to retain the BARC layer, it is typically desirable to remove the BARC layer through an etching process.
After patterning of the photoresist layer, various etchants may be selected to implement the removal of selected portions of material from the surface of the structure. Selectivity relates to the preservation of the surface underlying the etched material layer. The selectivity is generally expressed as a ratio of the etch rate of the material layer to the etch rate of the underlying surface. Further, selectivity may be used to refer to the removal rate of the photoresist with respect to the etched material layer. As can be appreciated, as the material layer is being etched through the openings patterned in the photoresist, some of the photoresist may also be removed. The removal of this photoresist during the etching procedure results in a less defined pattern in the etched layer, often increasing the critical dimensions of the integrated circuit. Accordingly, to minimize disadvantageous effects, the selectivity should be high enough to ensure that a substantial portion of the photoresist layer is not removed before the desired pattern is etched in the material layer.
As batches of semiconductor wafers are processed, the standard deviation of the critical dimensions of the features patterned on the semiconductor wafers may increase. This variance in the critical dimensions of the integrated circuits formed on semiconductor wafers is also referred to as critical dimension drift. As mentioned previously, integrated circuits have electrical properties that vary according to the critical dimensions. Therefore, it is important to keep these critical dimensions stable for as long as possible to achieve consistency in the electrical properties of the integrated circuits from batch to batch.